Spin-Up Sounds - NEC Vintage HardDrive
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EMC IP Holding Co LLC Original Assignee EMC Corp Priority date The priority date is an assumption and is not a legal conclusion.
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Assignors: BURROUGHS, JAMES V.
Assignors: BURROUGHS, JOHN V.
Assignors: EMC CORPORATION 2019-03-21 Assigned to THE BANK OF NEW YORK MELLON TRUST COMPANY, N.
SECURITY AGREEMENT Assignors: CREDANT TECHNOLOGIES, INC.
Spin-up of the drives is controlled by selectively delaying voltage inputs to the disk drives.
Alternately, spin-up of the drives is controlled by staggering the timing of communications to the disk drives.
Description CROSS REFERENCE TO RELATED APPLICATIONS This patent application is a Divisional of U.
FIELD OF THE INVENTION The present invention relates generally to disk drives and more particularly to controlling disk drive spin-ups in a multi-drive environment.
BACKGROUND As storage technologies advance, disk drives continue to become faster and cheaper.
As costs come down, computing, storage, and networking systems incorporate greater numbers of disk drives to maximize storage space and performance.
As the numbers of drives in a system increases, power budgets must be adjusted.
Current disk drives, such as hard disk drives and CD drives, rely on mechanically rotating disks for storage of information.
During operation, the disks rotate at very high rates of speed.
In systems containing many such disks, a large amount of power is required upon power-up and initialization to spin up the disks.
However, this large amount of power is required only during the time that the disks are accelerating.
Once brought up to speed, the disks require much less operational power.
In the past, power supply systems have been engineered to supply a large peak power to support disk spin-ups.
This solution is uneconomical in terms of space, thermal margin, and cost, especially in lower cost systems including multiple disk drives.
New disk drive controllers and drives that conform to the standard cause disk drives to spin up at different times, thus reducing required peak power.
This functionality, however, is provided only in the newest disk drives and chip sets.
It would be advantageous to be able to implement staggered drive spin-up in systems that utilize legacy disk drive controllers, in order to reduce peak power requirements and achieve the advantages of decreased space, improved thermal margin, and lower cost.
SUMMARY In accordance with the invention, disk drive spin-up is staggered to reduce peak power requirements.
According to one aspect of the invention, a first input voltage is provided to a first set of one or more disk drives and a second set of one or more disk drives.
A second input voltage that is different than the first input visit web page is also provided to the first set of disk drives.
The second input voltage is then provided to the second set a time interval after it is provided to the first set.
The first and second sets of one or more disk drives spin up after the provision of the second input voltage.
The spin-ups of the disk drives therefore occur at different times.
The first input voltage may be 12 Volts, while the second input voltage is 5 Volts.
The 5V input controls the disk drive communications electronics; thus, delaying the provision of the second input voltage causes the disk drive to delay spinning up.
In accordance with another aspect of the invention, disk drive spin-up is controlled by staggering communications to the disk drives.
A first device is coupled to a first disk drive via first disk communications lines.
The first device allows communications to be transferred to the first disk drive when a first reset signal is released.
A second device is coupled to a second disk drive via second disk communications lines.
The second device allows communications to be transferred to the second disk drive when a second reset signal is released.
A third device provides the first reset signal to the first device and the second reset signal to the second device so that the second reset signal is released a time interval after the first reset signal is released.
The first and second disk drives spin up after communications are received.
Since the communications are received at different times, the disk drives spin up at different times.
This aspect of the invention is particularly useful in highly available storage systems including redundant controllers that communicate with the disk drives staggered drive spin up reset capable multiplexers.
The various aspects of the invention are used to cause the multiple disk drives in a system to spin up at different times.
This allows a reduction in system peak power requirements, saving space, thermal budget, and cost in storage systems.
BRIEF DESCRIPTION OF THE DRAWINGS In order to facilitate a fuller understanding of the present invention, reference is now made to the appended drawings.
These drawings should not be construed as limiting the present invention, but are intended to be exemplary only.
DETAILED DESCRIPTION Referring to FIG.
The storage system 10 includes multiple disk drives 12 coupled to a controller module 14.
The controller module 14 includes one or more host controllers 16 and power circuit 18.
The power circuit 18 provides two different voltages, for example 12 Volt 12V power 20 and 5 Volt 5V power 22, to the disk drives 12.
The disk drives 12 use the different voltages for specific purposes.
For example, the 12V power 20 may be used to power the mechanical parts of the rotation drives, while the 5V power 22 can be used to power on-board electronics.
It is understood that other voltage values can be used without departing from the principles of the invention.
For example, some drives may continue reading their logic using 3.
The host controllers 16 and disk drives 12 communicate via communications signals 24, and in the case shown particularly via Transmit Tx and Receive Rx signals.
The disk drives 12 may be for example SATA Serial ATA drives and the host controllers 16 may be SATA host controllers.
Various types of host controllers are available to support differing numbers of drives.
For example, in a system such as 10 that includes twelve disk drives 12, three host controllers might be provided to support four drives each.
In a different embodiment, a host controller might support only one drive, and thus twelve host controllers 16 would be provided.
The principles of the invention apply to all such embodiments.
The communications may be click to see more example in the form of a command sequence.
When the drives 12 detect these commands, the drives spin up.
It is known, however, that the control logic within each disk drive 12 that responds to communications on the signal lines 24 is powered via the 5V power 22 to the drive 12.
Thus, if the 5V power 22 is not present, the drive 12 cannot respond to the commands from the host controller 16 and will not spin up.
The invention exploits this functionality by delaying the provision of the 5V power 22 to the drives 12 in a selective manner in order to stagger drive spin-up.
The power circuit 18 provides four 5V power outputs 22 a- d.
The power outputs 22 a are coupled to a first set 26 of three of the drives 12, the outputs 22 b are coupled to a next set 28 of three drives 12, and outputs 22 c and d are coupled to third and fourth sets 30 and 32 of three drives 12 respectively.
Referring also to FIG.
There may or may not be a delay between the provisions of 12V power and 5V power 22 a.
Then, after a delay t 1 step 38the 5V power 22 b is enabled to provide power to the second set 28 of three drives step 40.
After a delay t 2 step 42the 5V power 22 c is enabled to provide power to the third set 30 of three drives step 44.
And after a delay t 3 step 46the 5V power 22 d is enabled to provide power to the fourth set 32 of three drives step 48.
The delays t 1, t 2, t 3, and t 4 may be the same or different amounts of time, and may be provided staggered drive spin up separate timers or by a single timer with multiple outputs.
However implemented, the time interval between the successive applications of 5V power to the drives 12 is at least sufficient to allow completion of a drive spin-up sequence.
One implementation of the power sequencing of FIGS.
The power circuit 18 includes four voltage converters 50 a- 50 b, and four programmable delay components 52 a- 52 b.
The voltage converters can be for example Delta Electronics 12S2506A-1 converters.
The delay components 52 a- 52 b can be for example Maxim MAX6423XS22T components.
Each voltage converter 50 a- 50 d receives the 12V power 20 as input, and produces a corresponding 5V power 22 a- 22 d as output.
An article source signal 54 a- 54 d on each voltage converter 50 a- 50 d controllers the 5V output on each voltage converter 50 a- 50 d.
The 5V powers 22 a- 22 d are not provided unless the proper signal is received on the corresponding enable signal 54 a- 54 d.
Each programmable delay component 52 a- 52 d drives the corresponding enable signal 54 a- 54 d to the voltage converters 50 a- 50 d.
Each programmable delay component 52 a- 52 d is programmed to hold off the provision of its corresponding enable signal 54 a- 54 d in proportion to one of the delay times t 1-t 4.
Thus, the provision of 5V power 22 a- 22 d provided to the here sets of drives 26, 28, 30, and 32 is staggered in time.
For example, 12V and 5V power could be provided on separate rails rather than via a voltage converter.
Any sort of controller that can be programmed for delay could be coupled to enable separate 5V inputs to sets of drives.
Such a controller could be programmed in hardware via the configuration of inputs to provide the appropriate delays, or could be programmed via software to provide the delays.
The invention is thus not limited to any particular means of delaying 5V power to the drives.
Furthermore, though particular numbers of drives are described as powered up in sets, the invention is not limited to any particular numbers of drives, delayed power inputs, or controllers.
These numbers can be chosen flexibly in accordance with the particulars of a given design environment.
This storage system 60 is referred to as a highly available system.
Many redundancies are employed in a highly available system in order to avoid downtime to due to component and system failures.
In this storage system, two controller modules 41 a- 14 b are provided.
Each controller module 14 a- 14 b is coupled to the twelve disk drives 12 in a redundant manner.
There are twelve multiplexers 62 a- 62 l coupled between the controller modules 14 a- 14 b and each disk drive 12.
Each multiplexer 62 a- 62 l selectively supplies communications Tx and Rx signals 24 a- 24 b from the controller modules 14 a- 14 b to drive the disk communications Tx and Rx lines 64 a- 64 l to the disk drives 12.
In this manner, either one or the other of the controller modules 14 a- 14 b can access any disk drive 12 at any one time.
An arbiter 66 is coupled to the multiplexers 62 a- 62 l to control the access of the controller modules 14 a- 14 b to the disk drives 12.
The arbiter 66 drives a select line 68 to cause a multiplexer 62 to pass communications from either controller module 14 a or 14 b to the disk communications lines 64, or the arbiter 66 can drive a reset line 70 that causes the multiplexer 62 to pass no signals.
As previously described, the host controller s 16 on each controller module 14 a- 14 b will immediately attempt to send the standard SATA spin-up control sequence to the drives 12 upon power-up.
Once link drives receive this sequence, they spin up.
But, the drive will not spin up until the sequence is received.
In accordance with the principles of the invention, the provision of the SATA control sequence to the drives is selectively delayed in order to stagger disk drive spin-ups.
The arbiter 66 produces four reset signals Reset 70 a- 70 d.
Reset signals 70 a are coupled to a first set staggered drive spin up three multiplexers 72 a.
Reset signals 70 b are coupled to a second set of three multiplexers 72 b.
Likewise, Reset signals 70 c and 70 d are coupled to third and fourth sets 72 c and 72 d of multiplexers respectively.
The first set of multiplexers 72 a provides communication over communications lines 64 a- 64 c to the three disk drives of a first set 100 a of disk drives 12.
The second set of multiplexers 72 b provides communication over communications lines 64 d- 64 f to staggered drive spin up three disk drives of a second set 100 b of disk drives 12.
The third set of multiplexers 72 c provides communication over communications lines 64 g- 64 i to the three disk drives of a third set 100 c of disk drives 12.
The fourth set of multiplexers 72 d provides communication over communications lines 64 j- 64 l to the three disk drives of a fourth set 100 d of disk drives 12.
Upon power-up, the arbiter 66 asserts all four Reset signals 70 a- 70 d.
At this time, none of the multiplexers slots deposit bonus a- 72 d passes signals to the staggered drive spin up drive communication lines 64 a- 1.
Then, the Reset signals 70 a- 70 d are selectively released in a staggered manner in time.
Then, after a delay t 1 step 86the Reset signal 70 a is released step 88thus passing sequence commands from a host controller 16 on one of the modules 14 a- 14 b to the first set 100 a of disk drives via the multiplexers 72 a.
After a delay t 2 step 90the Reset signal 70 b is released step 92thus passing sequence commands from one of the controller modules 14 a- 14 b to the second set 100 b of disk drives via the multiplexers 72 b.
After a staggered drive spin up t 3 step 94the Reset signal 70 c is released step 96passing sequence commands from one of the controller modules 14 a- 14 b to the third set 100 c of disk drives.
And, after a delay t 4 step 98the Reset signal 70 d is released to provide sequence commands from a controller module 14 a- 14 b to the fourth set 100 d of three drives.
The delays t 1, t 2, t 3, and t 4 may be the same or different amounts of time, but each is at least sufficient to allow completion of a drive spin-up sequence.
In the implementation shown in FIG.
The arbiter can be custom designed and implemented in either an ASIC or a programmable logic device.
The arbiter is shown as a single device, but can be implemented as a series of separate arbiters that control multiplexers or groups of multiplexers without departing from the principles of the invention.
The design shown here utilizes four differently timed Reset signals to control groups of three disk drives; however, the numbers and arrangements of the example signals and components are not limited and are flexible in accordance with design requirements.
Furthermore, though this implementation describes a highly available storage system including two controller modules, the invention is equally applicable to systems without redundant controllers, such as the one shown in FIG.
In such a case, the multiplexer can be replaced with a simpler component that passes communications in response to the release of a signal such as a reset signal.
The present invention is not to be limited in scope by the specific embodiments described herein.
Indeed, various modifications of the present invention, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings.
Thus, such modifications are intended to fall within the scope of the invention.
Further, although aspects of the present invention have been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present invention can be beneficially implemented in any number of environments for any number of purposes.
Claims 8 a first device coupled to a first disk drive via first disk communications lines, the first device operable to receive click at this page first reset signal, the first device allowing communications to be transferred to the first disk drive when the first reset signal is released; a second device coupled to a second disk drive via second disk communications lines, the second device operable to receive a second reset signal, the second device allowing communications to be transferred to the second disk drive when the second reset signal is released; a third device for providing the first reset signal to the first device and the second reset signal to the second device, wherein the second reset signal is released a time interval after the first reset signal is released; a first controller module coupled to the first device and the second device via first module communications lines; and a second controller module coupled to the first device and the second device via second module communications lines; wherein the first device is operable to receive a first select signal and the second device is operable to receive a second select signal; and wherein the third device provides the first and second select signals, the first select signal for causing the first device to couple either the first module communications lines or the second module communications lines to the first disk communications lines, the second select signal for causing the second device to couple either the first module communications lines or the second module communications lines to the second disk communications lines.
Peak power validation methods and systems for non-volatile memory 2010-07-26 2014-09-02 Apple Inc.
Dynamic allocation of power budget to a system having non-volatile memory and a processor 2010-07-26 2013-10-08 Apple Inc.
Redundant power backplane for NAS storage device 2012-12-12 2016-08-09 Lenovo Enterprise Solutions Singapore Pte.
Disk system with activation control of disk drive motors 1998-05-06 2001-05-15 International Business Machines Corporation Smart DASD spin-up 2000-08-30 2002-02-28 Nec Corporation Power supply control system and power supply control method capable of reducing electric power consumption 2001-01-16 2003-12-23 Sun Microsystems, Inc.
Method and apparatus for the staggered startup of hard disk drives 2003-11-14 2005-05-19 Ming-Huan Yuan System and method for starting up plural electronic devices in an orderly manner 2001-12-13 2005-07-05 Seagate Technology Llc System for selectively controlling spin-up control for data storage devices in an array using predetermined out of band OOB signals 2004-03-01 2005-09-01 Yiu-Keung Ng Embedded power control circuitry for a portable disk drive carrier having a hot-plug application 2002-05-09 2005-11-15 International Business Machines Corporation Adaptive startup policy for accelerating multi-disk array spin-up 2003-04-01 2006-01-03 Dell Products L.
Coupling device for connectors wherein coupling device comprises multiplexer unit for selectiving first mode for SATA channel and second mode that establishes loop back function 2004-03-29 2006-04-18 Tecumseh Products Company Method and apparatus for reducing inrush current in a multi-stage compressor 2003-05-16 2007-02-06 Rackable Systems, Inc.
Computer rack with power distribution system 2003-12-29 2007-02-08 Sherwood Information Partners, Inc.
Disk system with activation control of disk drive motors 1994-07-19 1996-09-24 Intel Corporation Power management coordinator system and interface 1998-05-06 2001-05-15 International Business Machines Corporation Smart DASD spin-up 2000-08-30 2002-02-28 Nec Corporation Power supply control system and power supply control method capable of reducing electric power consumption 2000-08-30 2005-03-15 Nec Corporation System and method for controlling system power by sequentially controlling link initiating of a plurality of disk drive groups 2001-01-16 2003-12-23 Sun Microsystems, Inc.
Method and apparatus for the staggered startup of hard disk drives 2001-12-13 2005-07-05 Seagate Technology Llc System for selectively controlling spin-up control for data storage devices in an array using predetermined out of band OOB signals 2002-05-09 2005-11-15 International Business Machines Corporation Adaptive startup policy for accelerating multi-disk array spin-up 2003-04-01 2006-01-03 Dell Products L.
Coupling device for connectors wherein coupling device comprises multiplexer unit for selectiving first mode for SATA channel staggered drive spin up second mode that establishes loop back function 2003-05-16 2007-02-06 Rackable Systems, Inc.
Computer rack with power distribution system 2003-11-14 2005-05-19 Ming-Huan Yuan System and method for starting up plural electronic devices in an orderly manner 2003-12-29 2007-02-08 Sherwood Information Partners, Inc.
Methods and systems for optimized staggered disk drive spinup Also Published As Publication number Publication date 2007-12-04 Similar Documents Publication Publication Date Title 2013-04-30 Automated transitions power modes while continuously powering a power controller and powering down a media controller for at least one of the power modes 1999-07-06 Timer-controlled computer system shutdown and startup 2012-07-10 Electronic device and power saving method using predetermined command to designate portion of device in power saving mode 2014-01-14 Systems and methods for data throttling during disk drive power down 1996-12-17 Clock control unit responsive to a power management state for clocking multiple clocked circuits connected thereto 2009-02-24 Power throttling in a memory system 2002-02-05 Managing Vt for reduced power using a status table 2013-05-16 Nonvolatile storage system, power supply circuit for memory system, flash memory, flash memory controller, and nonvolatile semiconductor storage device 2000-10-10 Disk system and power-on sequence for the same 2008-07-01 Digital power manager for controlling and monitoring an array of point-of-load regulators 1999-07-20 Clock rate compensation for a low frequency slave device 2013-10-22 Adaptive power control 2006-12-21 Reducing computing system power through idle synchronization 2001-08-07 Method for entering powersave mode of USB hub 2003-08-19 Method and apparatus for reducing power consumption 2012-06-20 Multi-chip semiconductor memory device having an internal power supply voltage generation circuit to reduce the current consumption 1997-05-13 Method and apparatus for enhancing performance of a processor bmo harris atm deposit Method and apparatus for reducing power consumption in a computer system 2011-06-22 A semiconductor memory device 2002-05-21 Low-power apparatus for power management enabling 1997-07-29 Non-glitch clock switching circuit 2005-02-23 Data memory and processor bus 2017-08-22 Clock mode determination in a memory system 2013-10-22 Display interface buffer 1996-04-10 System and method for enabling and disabling a peripheral clock signal generator Legal Events Date Code Title Description 2007-12-10 AS Assignment Owner name: EMC CORPORATION, MASSACHUSETTS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BURROUGHS, JAMES V.
Vintage DEC RL-02 hard disk spin-up
• Hot-plug drive support • RAID Level Migration • Hot spares – global, dedicated, and pooled • Automatic/manual rebuild of hot spares • SES and SAF-TE enclosure management • Configurable stripe size • S.M.A.R.T. support • Multiple arrays per disk drive • Dynamic sector repair • Staggered drive spin-up • Bootable array.
Поздравляю, эта блестящая мысль придется как раз кстати
Мне очень жаль, что ничем не могу Вам помочь. Но уверен, что Вы найдёте правильное решение. Не отчаивайтесь.
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Весьма ценная информация
Я думаю, что Вы не правы. Давайте обсудим это. Пишите мне в PM, поговорим.
очень интересный и веселый!!!
Это не совсем то, что мне нужно. Кто еще, что может подсказать?
Да, бывает же...
Рекомендую Вам зайти на сайт, где есть много статей на интересующую Вас тему.
Вы допускаете ошибку. Могу отстоять свою позицию. Пишите мне в PM, обсудим.
По моему мнению Вы не правы. Давайте обсудим. Пишите мне в PM, поговорим.
Жалею, но ничего нельзя сделать.
Сенкс. Интересно, и вообще полезный у Вас блог